The invention relates generally to removal of metal in the formation of planarized interconnects for integrated circuits, and more particularly to method and apparatus for electro-removal, including generally electrochemical etching and particularly electropolishing.
Electropolishing is a method of polishing metal surfaces by applying an electric current through an electrolytic bath, as described for example in McGraw-Hill Encyclopedia of Science & Technology, pp. 810-811, 1982. The process is the reverse of electroplating. Anodic dissolution of surface features produces a flat, smooth, brilliant surface. Current density on the work surface is an important parameter. Below a certain voltage level, etching occurs. Above the etching voltage level, a constant current region is reached where polishing occurs. At even higher voltage, oxygen evolution interferes with polishing. The invention applies particularly to electropolishing, but can also be applied to electrolytic etching or electrochemical removal by varying the operating parameters from the polishing region.
In the fabrication of multilevel integrated circuit structures, the planarization of each metal layer, e.g., by pulsed laser or other heating as shown in U.S. Pat. Nos. 4,674,176 and 4,681,795 to Tuckerman, eliminates irregular and discontinuous conditions between successive layers, particularly where vias are located. To achieve fully planar multilevel interconnects, the dielectric layer must also be planarized, or the metal layer can be etched back so that it is flush with the dielectric layer.
U.S. Pat. No. 3,849,270 to Takagi et al. describes a process of manufacturing semiconductor devices using electrolytic etching to remove a coating layer from an insulating layer.
U.S. patent application Ser. No. 348,982 filed May 8, 1989, by Bernhardt et al. for Electrochemical Planarization describes a method and apparatus for forming a thin film planarized metal interconnect which is flush with the surrounding dielectric layer. In a preferred embodiment, a planarized metal layer is formed by controlled deposition, using an isotropic or other self-planarizing process, of a layer having a depth at least about half the width of the widest feature to be filled in the dielectric layer. The metal layer is then etched back by electropolishing.
In the electrochemical planarization process of U.S. patent application Ser. No. 348,982 filed May 8, 1989 is it essential that the etchback rate be substantially the same everywhere on the surface. The etchback process of preference is electropolishing because the etching rate can be high, the surface is polished (i.e. smoothed) in the process and the associated equipment is relatively inexpensive.